The present disclosure relates generally to integrated circuit test tools, and, in particular, to integrated circuit recovery testing using simulation checkpoints.
The testing of integrated circuits, such as application specific integrated circuits (ASICs), programmable logic devices (PLDs), microprocessors, microcontrollers, memory devices, and the like, includes the testing of resets such as power on reset and recovery reset. As used herein, the term power on reset refers to a full chip reset to establish the initial state of the integrated circuit. As used herein, the term recovery reset refers to a resetting of a subset of an integrated circuit to an initial state. Typically a recovery reset is applied to an area of logic that encountered an error condition. Recovery testing is often performed using a simulator interfacing with the integrated circuit being tested. As used herein, the term recovery testing refers to the testing of how well the integrated circuit is able to recover to a functional state from an error condition. The execution of a recovery test scenario can impact multiple portions of the simulation code because software queues and/or simulation expectations that have been set up during the simulation run need to be reset, and thus an in depth knowledge of the simulation code is required to implement a recovery test scenario. This can be challenging especially if the simulation code has been developed over many years with various code owners. It would be desirable to be able to reduce the coding effort required to implement a recovery test scenario.